An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications
ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings 2 (2003) 689-692
Abstract:
A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications
2003 INTERNATIONAL CONFERENCE ON MULTIMEDIA AND EXPO, VOL III, PROCEEDINGS (2003) 441-444
Reconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 49:4 (2003) 1383-1390