Publications by Philip Burrows


A fast, custom FPGA-based signal processor and its applications to intra-train beam stabilisation

Proceedings of the 11th International Workshop on Personal Computers and Particle Accelerator Controls, PCaPAC 2016 (2016) 137-140

GB Christian, NB Kraljevic, R Bodenstein, T Bromwich, PN Burrows, C Perry, R Ramjaiwan, J Roberts

Copyright © 2017 CC-BY-3.0 and by the respective authors. A custom 9-channel feedback controller has been developed for low-latency applications in beam-based stabilisation. Fast 14-bit ADCs and DACs are used for high-resolution signal conversion and a Xilinx Virtex-5 FPGA is used for core high-bandwidth digital computation. The sampling, and fast digital logic, can be clocked in the range 200 to 400 MHz, derived from an external or internal source. A custom data acquisition system, based around LabVIEW, has been developed for real-time control and monitoring at up to 460 kbps transfer rates, and is capable of writing and reading from EPICS data records. Details of the hardware, signal processing, and data acquisition will be presented. Two examples of applications will also be presented: a position and angle bunch-by-bunch feedback system using strip-line beam position monitors to stabilise intra-train positional jitter to below the micron level with a latency less than 154 ns; and a phase feedforward system using RF cavity-based phase monitors to stabilise the downstream rms phase jitter to below 50 fs with a total latency less than the 380 ns beam time-of-flight.


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